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Title: Unison : Publications

Description: Combinatorial Register Allocation and Instruction Scheduling

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Domain: unison-code.github.io

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Homehttps://unison-code.github.io/
Videoshttps://unison-code.github.io/videos.html
Publicationshttps://unison-code.github.io/publications.html
Downloadhttps://unison-code.github.io/download.html
Peoplehttps://unison-code.github.io/people.html
Fundinghttps://unison-code.github.io/funding.html
Combinatorial Register Allocation and Instruction Schedulinghttps://arxiv.org/abs/1804.02452
Register Allocation and Instruction Scheduling in Unisonhttp://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-183393
Combinatorial Spill Code Optimization and Ultimate Coalescinghttp://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-154398
Constraint-based Code Generationhttp://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-125069
Constraint-based Register Allocation and Instruction Schedulinghttp://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-104554
Register Allocation and Instruction Scheduling in Unisonhttps://www.sics.se/%7ercas/presentations/llvm2017.pdf
[YouTube]https://www.youtube.com/watch?v=kx64V74Mba0
Modeling and Solving Code Generation for Realhttp://www.gecode.org/~schulte/talks/Code%20Generation%20KTH%202016.pdf
Optimal Register Allocation and Instruction Scheduling for LLVMhttps://www.sics.se/%7ercas/presentations/llvm2016.pdf
[YouTube]https://www.youtube.com/watch?v=TkanbGAG_Fo
Integrated Register Allocation and Instruction Scheduling with Constraint Programminghttps://www.sics.se/%7ercas/presentations/lic2014.pdf
Rethinking Code Generation in Compilershttp://www.gecode.org/~schulte//talks/ECS%202014.pdf
Combinatorial Spill Code Optimization and Ultimate Coalescinghttps://www.sics.se/%7ercas/presentations/lctes2014.pdf
Unison: Assembly Code Generation Using Constraint Programminghttps://www.sics.se/%7ercas/presentations/date2014.pdf
Constraint-based Code Generationhttps://www.sics.se/%7ercas/presentations/mscopes2013.pdf
Constraint-based Register Allocation and Instruction Schedulinghttps://www.sics.se/%7ercas/presentations/cp2012.pdf
Constraint-Based Register Allocation and Instruction Schedulinghttp://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-232192
Evaluating Unison’s Speedup Estimationhttp://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-210647
Evaluation and Implementation of Dominance Breaking Presolving Techniques in the Unison Compiler Back-Endhttp://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175835
Implied Constraints for the Unison Presolverhttp://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175838
Integrated Register Allocation and Instruction Scheduling with Constraint Programminghttp://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-154599
Necessary Conditions for Constraint-based Register Allocation and Instruction Schedulinghttp://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-209267

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