Title: GitHub · Where software is built
Open Graph Title: rstar900/Dual-Core-RISC-V-Processor
X Title: rstar900/Dual-Core-RISC-V-Processor
Description: A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board. - rstar900/Dual-Core-RISC-V-Processor
Open Graph Description: A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board. - rstar900/Dual-Core-RISC-V-Processor
X Description: A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board. - rstar900/Dual-Core-RISC-V-Processor
Opengraph URL: https://github.com/rstar900/Dual-Core-RISC-V-Processor
X: @github
Domain: patch-diff.githubusercontent.com
| route-pattern | /:user_id/:repository/issues(.:format) |
| route-controller | issues |
| route-action | index |
| fetch-nonce | v2:f757b0b5-26dd-199e-dbd1-34656567e7a1 |
| current-catalog-service-hash | 81bb79d38c15960b92d99bca9288a9108c7a47b18f2423d0f6438c5b7bcd2114 |
| request-id | BDC8:B0221:2CFEEB:3C02F3:698EDD3C |
| html-safe-nonce | 4f178f2455a329e99cef279b80ab77cede4b56608cadecce81121910dd55a5e1 |
| visitor-payload | eyJyZWZlcnJlciI6IiIsInJlcXVlc3RfaWQiOiJCREM4OkIwMjIxOjJDRkVFQjozQzAyRjM6Njk4RUREM0MiLCJ2aXNpdG9yX2lkIjoiNTA4MjUxNTk4MTc1MTczNzY2MCIsInJlZ2lvbl9lZGdlIjoiaWFkIiwicmVnaW9uX3JlbmRlciI6ImlhZCJ9 |
| visitor-hmac | 17d1928a3f4924cf651a5c5d6691f32aa561f3480994a61b0b8e193a538bbdc2 |
| hovercard-subject-tag | repository:522245283 |
| github-keyboard-shortcuts | repository,issues,copilot |
| google-site-verification | Apib7-x98H0j5cPqHWwSMm6dNU4GmODRoqxLiDzdx9I |
| octolytics-url | https://collector.github.com/github/collect |
| analytics-location | / |
| fb:app_id | 1401488693436528 |
| apple-itunes-app | app-id=1477376905, app-argument=https://github.com/rstar900/Dual-Core-RISC-V-Processor/issues |
| twitter:image | https://opengraph.githubassets.com/17845f403f1369e35dc6304127ed69d1143e16a6638728ae6b12daf901d44ca7/rstar900/Dual-Core-RISC-V-Processor |
| twitter:card | summary_large_image |
| og:image | https://opengraph.githubassets.com/17845f403f1369e35dc6304127ed69d1143e16a6638728ae6b12daf901d44ca7/rstar900/Dual-Core-RISC-V-Processor |
| og:image:alt | A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board. - rstar900/Dual-Core-RISC-V-Processor |
| og:image:width | 1200 |
| og:image:height | 600 |
| og:site_name | GitHub |
| og:type | object |
| hostname | github.com |
| expected-hostname | github.com |
| None | cb2828a801ee6b7be618f3ac76fbf55def35bbc30f053a9c41bf90210b8b72ba |
| turbo-cache-control | no-cache |
| go-import | github.com/rstar900/Dual-Core-RISC-V-Processor git https://github.com/rstar900/Dual-Core-RISC-V-Processor.git |
| octolytics-dimension-user_id | 25794033 |
| octolytics-dimension-user_login | rstar900 |
| octolytics-dimension-repository_id | 522245283 |
| octolytics-dimension-repository_nwo | rstar900/Dual-Core-RISC-V-Processor |
| octolytics-dimension-repository_public | true |
| octolytics-dimension-repository_is_fork | false |
| octolytics-dimension-repository_network_root_id | 522245283 |
| octolytics-dimension-repository_network_root_nwo | rstar900/Dual-Core-RISC-V-Processor |
| turbo-body-classes | logged-out env-production page-responsive |
| disable-turbo | false |
| browser-stats-url | https://api.github.com/_private/browser/stats |
| browser-errors-url | https://api.github.com/_private/browser/errors |
| release | e6b91a7e6e46287d26887e3fb7a4161657bab8f7 |
| ui-target | full |
| theme-color | #1e2327 |
| color-scheme | light dark |
Links:
Viewport: width=device-width