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Title: GitHub - rstar900/Dual-Core-RISC-V-Processor: A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.

Open Graph Title: GitHub - rstar900/Dual-Core-RISC-V-Processor: A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.

X Title: GitHub - rstar900/Dual-Core-RISC-V-Processor: A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.

Description: A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board. - rstar900/Dual-Core-RISC-V-Processor

Open Graph Description: A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board. - rstar900/Dual-Core-RISC-V-Processor

X Description: A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board. - rstar900/Dual-Core-RISC-V-Processor

Opengraph URL: https://github.com/rstar900/Dual-Core-RISC-V-Processor

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