Title: GitHub - pulp-platform/axi: AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Open Graph Title: GitHub - pulp-platform/axi: AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
X Title: GitHub - pulp-platform/axi: AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Description: AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication - pulp-platform/axi
Open Graph Description: AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication - pulp-platform/axi
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