René's URL Explorer Experiment

{"@context":"https://schema.org","@type":"DiscussionForumPosting","headline":"can't build: `ValueError: Cannot extract CSR name from code, need to specify.`","articleBody":"Hi,\nI tried to follow the readme, but gateware build failed. Please see stdout below:\n\n\u003cdetails\u003e\n\n\u003csummary\u003epdm install\u003c/summary\u003e\n\n```\nINFO: The saved Python interpreter does not exist or broken. Trying to find another one.\nWARNING: Project requires a python version of \u003e=3.10, The virtualenv is being created for you as it cannot be matched to the right version.\nINFO: python.use_venv is on, creating a virtualenv for this project...\nVirtualenv is created successfully at /home/user/Downloads/orbtrace/.venv\nSynchronizing working set with resolved packages: 32 to add, 0 to update, 0 to remove\n\n  ✔ Install iniconfig 2.0.0 successful\n  ✔ Install litehyperbus 0.0.0 successful\n  ✔ Install idna 3.10 successful\n  ✔ Install litespi 0.0.0 successful\n  ✔ Install pluggy 1.5.0 successful\n  ✔ Install colorama 0.4.6 successful\n  ✔ Install packaging 24.2 successful\n  ✔ Install construct 2.10.70 successful\n  ✔ Install certifi 2025.1.31 successful\n  ✔ Install pyvcd 0.4.1 successful\n  ✔ Install jinja2 3.1.5 successful\n  ✔ Install pyusb 1.3.1 successful\n  ✔ Install cobs 1.2.2 successful\n  ✔ Install jschon 0.11.1 successful\n  ✔ Install amaranth 0.5.4 successful\n  ✔ Install requests 2.32.3 successful\n  ✔ Install pyserial 3.5 successful\n  ✔ Install libusb1 3.2.0 successful\n  ✔ Install rfc3986 2.0.0 successful\n  ✔ Install usb-protocol 0.9.1 successful\n  ✔ Install migen 0.9.2 successful\n  ✔ Install pytest 9.0.2 successful\n  ✔ Install luna-usb 0.2.0 successful\n  ✔ Install urllib3 2.3.0 successful\n  ✔ Install litex-boards 0.0.0 successful\n  ✔ Install markupsafe 3.0.2 successful\n  ✔ Install pygments 2.19.2 successful\n  ✔ Install charset-normalizer 3.4.1 successful\n  ✔ Install litex 2023.12 successful\n  ✔ Install pythondata-cpu-vexriscv 1.0.1.post407 successful\n  ✔ Install pythondata-software-compiler-rt 0.0.post6206 successful\n  ✔ Install pythondata-software-picolibc 1.7.9.post181 successful\n  ✔ Install orbtrace 1.4.4.dev1+gca2149e.d20251226 successful\n\n  0:00:03 🎉 All complete! 32/32\n```\n\u003c/details\u003e\n\n`source .venv/bin/activate.fish`\n\n\n\n\u003cdetails\u003e\n\n\u003csummary\u003epdm run orbtrace_builder --platform orbtrace_mini --build\u003c/summary\u003e\n\n```\n/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/integration/export.py:100: SyntaxWarning: invalid escape sequence '\\d'\n  version = float(re.findall(\"\\d+\\.\\d+\", l)[-1])\n/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cva6/core.py:47: SyntaxWarning: invalid escape sequence '\\$'\n  res = re.search('\\$\\{(CVA6_REPO_DIR|LX_CVA6_CORE_DIR)\\}/(.+)', l)\n/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cva6/core.py:53: SyntaxWarning: invalid escape sequence '\\+'\n  if re.match('\\+incdir\\+', l):\n/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/openc906/core.py:64: SyntaxWarning: invalid escape sequence '\\$'\n  res = re.search('\\$\\{CODE_BASE_PATH\\}/(.+)', l)\n/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/openc906/core.py:66: SyntaxWarning: invalid escape sequence '\\+'\n  if re.match('\\+incdir\\+', l):\n/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cv32e41p/core.py:67: SyntaxWarning: invalid escape sequence '\\$'\n  res = re.search('\\$\\{DESIGN_RTL_DIR\\}/(.+)', l)\n/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cv32e41p/core.py:69: SyntaxWarning: invalid escape sequence '\\+'\n  if re.match('\\+incdir\\+', l):\n/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cv32e40p/core.py:80: SyntaxWarning: invalid escape sequence '\\$'\n  res = re.search('\\$\\{DESIGN_RTL_DIR\\}/(.+)', l)\n/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/cores/cpu/cv32e40p/core.py:82: SyntaxWarning: invalid escape sequence '\\+'\n  if re.match('\\+incdir\\+', l):\nINFO:SoC:        __   _ __      _  __  \nINFO:SoC:       / /  (_) /____ | |/_/  \nINFO:SoC:      / /__/ / __/ -_)\u003e  \u003c    \nINFO:SoC:     /____/_/\\__/\\__/_/|_|  \nINFO:SoC:  Build your hardware, easily!\nINFO:SoC:--------------------------------------------------------------------------------\nINFO:SoC:Creating SoC... (2025-12-26 23:58:06)\nINFO:SoC:--------------------------------------------------------------------------------\nINFO:SoC:FPGA device : LFE5U-25F-8BG256C.\nINFO:SoC:System clock: 75.000MHz.\nINFO:SoCBusHandler:Creating Bus Handler...\nINFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.\nINFO:SoCBusHandler:Adding reserved Bus Regions...\nINFO:SoCBusHandler:Bus Handler created.\nINFO:SoCCSRHandler:Creating CSR Handler...\nINFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).\nINFO:SoCCSRHandler:Adding reserved CSRs...\nINFO:SoCCSRHandler:CSR Handler created.\nINFO:SoCIRQHandler:Creating IRQ Handler...\nINFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).\nINFO:SoCIRQHandler:Adding reserved IRQs...\nINFO:SoCIRQHandler:IRQ Handler created.\nINFO:SoC:--------------------------------------------------------------------------------\nINFO:SoC:Initial SoC:\nINFO:SoC:--------------------------------------------------------------------------------\nINFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.\nINFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).\nINFO:SoC:IRQ Handler (up to 32 Locations).\nINFO:SoC:--------------------------------------------------------------------------------\nINFO:SoC:Controller ctrl added.\nTraceback (most recent call last):\n  File \"/home/user/Downloads/orbtrace/.venv/bin/orbtrace_builder\", line 8, in \u003cmodule\u003e\n    sys.exit(main())\n             ~~~~^^\n  File \"/home/user/Downloads/orbtrace/orbtrace_builder.py\", line 78, in main\n    soc = OrbSoC(\n        platform = platform,\n    ...\u003c11 lines\u003e...\n        **soc_core_argdict(args)\n    )\n  File \"/home/user/Downloads/orbtrace/orbtrace/soc.py\", line 51, in __init__\n    SoCCore.__init__(self, platform, sys_clk_freq,\n    ~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n        ident          = 'LiteX SoC for Orbtrace',\n        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n        **kwargs)\n        ^^^^^^^^^\n  File \"/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/integration/soc_core.py\", line 208, in __init__\n    self.add_controller(\"ctrl\")\n    ~~~~~~~~~~~~~~~~~~~^^^^^^^^\n  File \"/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/integration/soc.py\", line 992, in add_controller\n    self.add_module(name=name, module=SoCController(**kwargs))\n                                      ~~~~~~~~~~~~~^^^^^^^^^^\n  File \"/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/integration/soc.py\", line 831, in __init__\n    self._reset = CSRStorage(fields=[\n                  ~~~~~~~~~~^^^^^^^^^\n        CSRField(\"soc_rst\", size=1, offset=0, pulse=True, description=\"\"\"Write `1` to this register to reset the full SoC (Pulse Reset)\"\"\"),\n        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n        CSRField(\"cpu_rst\", size=1, offset=1,             description=\"\"\"Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset)\"\"\"),\n        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n    ])\n    ^^\n  File \"/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/interconnect/csr.py\", line 388, in __init__\n    _CompoundCSR.__init__(self, size, name, n)\n    ~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^\n  File \"/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/interconnect/csr.py\", line 136, in __init__\n    _CSRBase.__init__(self, size, name, n)\n    ~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^\n  File \"/home/user/Downloads/orbtrace/.venv/lib/python3.13/site-packages/litex/soc/interconnect/csr.py\", line 53, in __init__\n    raise ValueError(\"Cannot extract CSR name from code, need to specify.\")\nValueError: Cannot extract CSR name from code, need to specify.\n```\n\u003c/details\u003e\n\nMaybe something changed in litex?","author":{"url":"https://github.com/diggit","@type":"Person","name":"diggit"},"datePublished":"2025-12-26T23:04:49.000Z","interactionStatistic":{"@type":"InteractionCounter","interactionType":"https://schema.org/CommentAction","userInteractionCount":1},"url":"https://github.com/29/orbtrace/issues/29"}