Title: Sanjaydulipudi (DULIPUDI LAASHMITH SANJAY) Β· GitHub
Open Graph Title: Sanjaydulipudi - Overview
X Title: Sanjaydulipudi - Overview
Description: π Final-Year B.Tech (ECE) Student | Vasireddy Venkatadri Institute of Technology π¬ VLSI Enthusiast | RTL Design & Physical Design | Verilog | SystemVerilog - Sanjaydulipudi
Open Graph Description: π Final-Year B.Tech (ECE) Student | Vasireddy Venkatadri Institute of Technology π¬ VLSI Enthusiast | RTL Design & Physical Design | Verilog | SystemVerilog - Sanjaydulipudi
X Description: π Final-Year B.Tech (ECE) Student | Vasireddy Venkatadri Institute of Technology π¬ VLSI Enthusiast | RTL Design & Physical Design | Verilog | SystemVerilog - Sanjaydulipudi
Opengraph URL: https://github.com/Sanjaydulipudi
X: @github
Domain: patch-diff.githubusercontent.com
| route-pattern | /:user_id(.:format) |
| route-controller | profiles |
| route-action | show |
| fetch-nonce | v2:e5935983-69ac-70cd-9048-a4a9af02651e |
| current-catalog-service-hash | 4a1c50a83cf6cc4b55b6b9c53e553e3f847c876b87fb333f71f5d05db8f1a7db |
| request-id | DDE4:46ACF:1A24D50:239E3FD:698C6FC9 |
| html-safe-nonce | 275bc50b7a6699ab4e30b5a9679f9240b5d1dcf177d9fe3ef9254b0d9801e937 |
| visitor-payload | eyJyZWZlcnJlciI6IiIsInJlcXVlc3RfaWQiOiJEREU0OjQ2QUNGOjFBMjRENTA6MjM5RTNGRDo2OThDNkZDOSIsInZpc2l0b3JfaWQiOiI4MTg1Njg5MzcyNzY4MzY2NTM3IiwicmVnaW9uX2VkZ2UiOiJpYWQiLCJyZWdpb25fcmVuZGVyIjoiaWFkIn0= |
| visitor-hmac | b7f02cfb2296ba623102552de646335d11780fa4dc8914304d227d9a29055298 |
| github-keyboard-shortcuts | copilot |
| google-site-verification | Apib7-x98H0j5cPqHWwSMm6dNU4GmODRoqxLiDzdx9I |
| octolytics-url | https://collector.github.com/github/collect |
| analytics-location | / |
| fb:app_id | 1401488693436528 |
| apple-itunes-app | app-id=1477376905, app-argument=https://github.com/Sanjaydulipudi |
| twitter:image | https://avatars.githubusercontent.com/u/168713019?v=4?s=400 |
| twitter:card | summary |
| og:image | https://avatars.githubusercontent.com/u/168713019?v=4?s=400 |
| og:image:alt | π Final-Year B.Tech (ECE) Student | Vasireddy Venkatadri Institute of Technology π¬ VLSI Enthusiast | RTL Design & Physical Design | Verilog | SystemVerilog - Sanjaydulipudi |
| og:site_name | GitHub |
| og:type | profile |
| profile:username | Sanjaydulipudi |
| hostname | github.com |
| expected-hostname | github.com |
| None | 640eeb7b6ff4d8d106235d228c0c286e82592d4d2403227b5b2b4fc5832297a4 |
| turbo-cache-control | no-preview |
| octolytics-dimension-user_id | 168713019 |
| octolytics-dimension-user_login | Sanjaydulipudi |
| turbo-body-classes | logged-out env-production page-responsive page-profile |
| disable-turbo | false |
| browser-stats-url | https://api.github.com/_private/browser/stats |
| browser-errors-url | https://api.github.com/_private/browser/errors |
| release | 3d444f0a47beeeac94cddbb51c91ab408befe8d4 |
| ui-target | full |
| theme-color | #1e2327 |
| color-scheme | light dark |
Links:
Viewport: width=device-width