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Title: GitHub - DispatchCode/x64-Instruction-Decoder: An x86/x64 instruction disassembler written in C

Open Graph Title: GitHub - DispatchCode/x64-Instruction-Decoder: An x86/x64 instruction disassembler written in C

X Title: GitHub - DispatchCode/x64-Instruction-Decoder: An x86/x64 instruction disassembler written in C

Description: An x86/x64 instruction disassembler written in C. Contribute to DispatchCode/x64-Instruction-Decoder development by creating an account on GitHub.

Open Graph Description: An x86/x64 instruction disassembler written in C. Contribute to DispatchCode/x64-Instruction-Decoder development by creating an account on GitHub.

X Description: An x86/x64 instruction disassembler written in C. Contribute to DispatchCode/x64-Instruction-Decoder development by creating an account on GitHub.

Opengraph URL: https://github.com/DispatchCode/x64-Instruction-Decoder

X: @github

direct link

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og:image:altAn x86/x64 instruction disassembler written in C. Contribute to DispatchCode/x64-Instruction-Decoder development by creating an account on GitHub.
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[1]https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#user-content-res1
x64ID ~ x64 Instruction Decoderhttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#x64id--machine-code-analyzer
Supported architectures and featureshttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#supported-architectures-and-features
Features on developmenthttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#features-on-development
APIhttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#api
Instruction structhttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#instruction-struct
REX unionhttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#rex-union
ModRm unionhttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#modrm-union
SIB unionhttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#sib-union
vex_info structhttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#vex_info-struct
Exampleshttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#examples
A practical example: sum of two vectors using SIMD instructionhttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#a-practical-example-sum-of-two-vectors-using-simd-instruction
Another example: architecture x64, VEX prefix with YMM registerhttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#another-example-architecture-x64-vex-prefix-with-ymm-register
Enabling / Disabling featureshttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#enabling--disabling-features
Function Length detectionhttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#find-function-length
Testshttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#tests
Useful resourceshttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#useful-resources
Noteshttps://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#notes
https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#supported-architectures-and-features
https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#features-on-development
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https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#examples
https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#a-practical-example-sum-of-two-vectors-using-simd-instruction
https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#another-example-architecture-x64-vex-prefix-with-ymm-register
https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#enabling--disabling-features
https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#find-length-of-a-function
https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#tests
[2]https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#user-content-res2
https://patch-diff.githubusercontent.com/DispatchCode/x64-Instruction-Decoder#useful-resources
X86-64 Instruction Encodinghttps://wiki.osdev.org/X86-64_Instruction_Encoding
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