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Title: GitHub - lowRISC/sail: Sail architecture definition language

Open Graph Title: GitHub - lowRISC/sail: Sail architecture definition language

X Title: GitHub - lowRISC/sail: Sail architecture definition language

Description: Sail architecture definition language. Contribute to lowRISC/sail development by creating an account on GitHub.

Open Graph Description: Sail architecture definition language. Contribute to lowRISC/sail development by creating an account on GitHub.

X Description: Sail architecture definition language. Contribute to lowRISC/sail development by creating an account on GitHub.

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CHANGELOG.mdhttps://github.com/lowRISC/sail/blob/sail2/CHANGELOG.md
CHANGELOG.mdhttps://github.com/lowRISC/sail/blob/sail2/CHANGELOG.md
Dockerfile.nightlyhttps://github.com/lowRISC/sail/blob/sail2/Dockerfile.nightly
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Makefilehttps://github.com/lowRISC/sail/blob/sail2/Makefile
README.mdhttps://github.com/lowRISC/sail/blob/sail2/README.md
README.mdhttps://github.com/lowRISC/sail/blob/sail2/README.md
THIRD_PARTY_FILES.mdhttps://github.com/lowRISC/sail/blob/sail2/THIRD_PARTY_FILES.md
THIRD_PARTY_FILES.mdhttps://github.com/lowRISC/sail/blob/sail2/THIRD_PARTY_FILES.md
docker_entry_point.shhttps://github.com/lowRISC/sail/blob/sail2/docker_entry_point.sh
docker_entry_point.shhttps://github.com/lowRISC/sail/blob/sail2/docker_entry_point.sh
dune-projecthttps://github.com/lowRISC/sail/blob/sail2/dune-project
dune-projecthttps://github.com/lowRISC/sail/blob/sail2/dune-project
libsail.opamhttps://github.com/lowRISC/sail/blob/sail2/libsail.opam
libsail.opamhttps://github.com/lowRISC/sail/blob/sail2/libsail.opam
sailhttps://github.com/lowRISC/sail/blob/sail2/sail
sailhttps://github.com/lowRISC/sail/blob/sail2/sail
sail.opamhttps://github.com/lowRISC/sail/blob/sail2/sail.opam
sail.opamhttps://github.com/lowRISC/sail/blob/sail2/sail.opam
sail.opam.templatehttps://github.com/lowRISC/sail/blob/sail2/sail.opam.template
sail.opam.templatehttps://github.com/lowRISC/sail/blob/sail2/sail.opam.template
sail_c_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_c_backend.opam
sail_c_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_c_backend.opam
sail_coq_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_coq_backend.opam
sail_coq_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_coq_backend.opam
sail_doc_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_doc_backend.opam
sail_doc_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_doc_backend.opam
sail_latex_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_latex_backend.opam
sail_latex_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_latex_backend.opam
sail_lem_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_lem_backend.opam
sail_lem_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_lem_backend.opam
sail_manifest.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_manifest.opam
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sail_output.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_output.opam
sail_output.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_output.opam
sail_smt_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_smt_backend.opam
sail_smt_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_smt_backend.opam
sail_sv_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_sv_backend.opam
sail_sv_backend.opamhttps://github.com/lowRISC/sail/blob/sail2/sail_sv_backend.opam
READMEhttps://github.com/lowRISC/sail
Licensehttps://github.com/lowRISC/sail
https://github.com/rems-project/sail/blob/sail2/etc/logo/sail_logo.png?raw=true
https://github.com/lowRISC/sail#the-sail-isa-specification-language
https://github.com/rems-project/sail/actions/workflows/build.yml
https://github.com/lowRISC/sail#overview
CHERI ISAv9https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-987.pdf#page=176
CHERIoThttps://www.microsoft.com/en-us/research/uploads/prod/2023/02/cheriot-63e11a4f1e629.pdf#page=91
Sail AsciiDoctor documentation for RISC-Vhttps://github.com/Alasdair/asciidoctor-sail/blob/master/doc/built/sail_to_asciidoc.pdf
isla-axiomatichttps://github.com/rems-project/isla
RMEMhttp://www.cl.cam.ac.uk/users/pes20/rmem
Islahttps://github.com/rems-project/isla
proofs for the Arm Morello ISAhttp://www.cl.cam.ac.uk/~pes20/morello-proofs-esop2022.pdf
Islarishttps://github.com/rems-project/islaris
https://github.com/rems-project/sail/blob/sail2/etc/overview/overview-sail.png?raw=true
https://github.com/lowRISC/sail#sail-isa-models
Sail Arm-A (from ASL)https://github.com/rems-project/sail-arm
Sail Armv8.3-Ahttps://github.com/rems-project/sail/tree/sail2/aarch64
POPL 2019 paperhttp://www.cl.cam.ac.uk/users/pes20/sail/sail-popl2019.pdf
handwritten Sail Armv8-A ISA modelhttps://github.com/rems-project/sail/tree/sail2/aarch64_small
Sail Morello (CHERI-Arm) (from ASL)https://github.com/CTSRD-CHERI/sail-morello
Morello security proofshttps://github.com/CTSRD-CHERI/sail-morello-proofs/blob/public/README.md
Sail RISC-Vhttps://github.com/riscv/sail-riscv
Sail CHERI RISC-Vhttps://github.com/CTSRD-CHERI/sail-cheri-riscv
CHERIhttps://www.cl.cam.ac.uk/research/security/ctsrd/cheri/
Sail CHERIoThttps://github.com/microsoft/cheriot-sail
CHERIoThttps://www.microsoft.com/en-us/research/publication/cheriot-rethinking-security-for-low-cost-embedded-systems/
Sail x86 (from ACL2)https://github.com/rems-project/sail-x86-from-acl2
X86isahttps://www.cs.utexas.edu/users/moore/acl2/manuals/current/manual/index-seo.php/ACL2____X86ISA
Sail MIPS and CHERI-MIPShttps://github.com/CTSRD-CHERI/sail-cheri-mips
CHERIhttps://www.cl.cam.ac.uk/research/security/ctsrd/cheri/
Sail IBM POWER (from IBM XML)https://github.com/rems-project/sail/tree/sail2/old/power
Sail x86 (legacy)https://github.com/rems-project/sail/tree/sail2/old/x86
https://github.com/lowRISC/sail#example
https://github.com/lowRISC/sail#this-repository
doc/manual.htmlhttps://github.com/lowRISC/sail/blob/sail2/doc/manual.html
doc/https://github.com/lowRISC/sail/blob/sail2/doc
available online herehttps://alasdair.github.io/manual.html
src/https://github.com/lowRISC/sail/blob/sail2/src
snapshots/isabellehttps://github.com/lowRISC/sail/blob/sail2/snapshots/isabelle
lib/isabelle/manual.pdfhttps://github.com/lowRISC/sail/blob/sail2/lib/isabelle/manual.pdf
editors/https://github.com/lowRISC/sail/blob/sail2/editors
test/https://github.com/lowRISC/sail/blob/sail2/test
a separate repositoryhttps://github.com/rems-project/coq-sail
https://github.com/lowRISC/sail#installation
INSTALL.mdhttps://github.com/lowRISC/sail/blob/sail2/INSTALL.md
https://github.com/lowRISC/sail#editor-support
editors/sail-mode.elhttps://github.com/lowRISC/sail/blob/sail2/editors/sail-mode.el
editors/vscodehttps://github.com/lowRISC/sail/blob/sail2/editors/vscode
editors/vscode/sailhttps://github.com/lowRISC/sail/blob/sail2/editors/vscode/sail
editors/vscode/sail/syntax/sail.tmLanguage.jsonhttps://github.com/lowRISC/sail/blob/sail2/sail.tmLanguage.json
editors/vscode/sailhttps://github.com/lowRISC/sail/blob/sail2/editors/vscode/sail
TextMate Bundles pluginhttps://plugins.jetbrains.com/plugin/7221-textmate-bundles
editors/vimhttps://github.com/lowRISC/sail/blob/sail2/editors/vim
https://github.com/lowRISC/sail#logo
etc/logohttps://github.com/lowRISC/sail/blob/sail2/etc/logo
CC0https://creativecommons.org/publicdomain/zero/1.0/
https://github.com/lowRISC/sail#licensing
https://github.com/meriac/archexhttps://github.com/meriac/archex
README filehttps://github.com/lowRISC/sail/blob/sail2/aarch64/README
https://github.com/lowRISC/sail#people
Alasdair Armstrong http://alasdair.io/
Thomas Bauereiss http://www.cl.cam.ac.uk/~tb592
Brian Campbell http://homepages.inf.ed.ac.uk/bcampbe2/
Shaked Flur http://www.cl.cam.ac.uk/~sf502
Neel Krishnaswami http://www.cl.cam.ac.uk/~nk480/
Christopher Pulte http://www.cl.cam.ac.uk/~cp526/
Alastair Reid https://alastairreid.github.io/
Peter Sewell http://www.cl.cam.ac.uk/~pes20
Ian Stark http://homepages.inf.ed.ac.uk/stark/
Jon French http://www.cl.cam.ac.uk/~jf451/
Kathryn E. Gray http://www.cl.cam.ac.uk/~keg29/
Gabriel Kerneis http://gabriel.kerneis.info/
Prashanth Mundkur http://www.csl.sri.com/people/mundkur/
Robert Norton-Wright http://www.cl.cam.ac.uk/~rmn30/
Mark Wassell http://www.cl.cam.ac.uk/~mpew2
CHERIhttps://www.cl.cam.ac.uk/research/security/ctsrd/cheri/
CHERIoThttps://www.microsoft.com/en-us/research/publication/cheriot-rethinking-security-for-low-cost-embedded-systems/
https://github.com/lowRISC/sail#papers
POPL 2019 paperhttp://www.cl.cam.ac.uk/users/pes20/sail/sail-popl2019.pdf
Multicore Semantics: Making Sense of Relaxed Memory (MPhil slides)https://www.cl.cam.ac.uk/~pes20/slides-acs-2022.pdf
bibhttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_bib.html#acs-2020
.pdfhttps://www.cl.cam.ac.uk/~pes20/slides-acs-2022.pdf
Islaris: Verification of Machine Code Against Authoritative ISA Semanticshttp://www.cl.cam.ac.uk/~pes20/2022-pldi-islaris.pdf
bibhttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_bib.html#2022-pldi-islaris
doihttp://dx.doi.org/10.1145/3519939.3523434
project pagehttps://github.com/rems-project/islaris
pdfhttp://www.cl.cam.ac.uk/~pes20/2022-pldi-islaris.pdf
abstracthttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_abstracts.html#2022-pldi-islaris
Verified Security for the Morello Capability-enhanced Prototype Arm Architecturehttp://www.cl.cam.ac.uk/~pes20/morello-proofs-esop2022.pdf
bibhttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_bib.html#morello-proofs-esop2022
doihttp://dx.doi.org/10.1007/978-3-030-99336-8\_7
project pagehttps://www.cl.cam.ac.uk/research/security/ctsrd/cheri/
pdfhttp://www.cl.cam.ac.uk/~pes20/morello-proofs-esop2022.pdf
httphttps://doi.org/10.1007/978-3-030-99336-8\_7
abstracthttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_abstracts.html#morello-proofs-esop2022
Isla: Integrating full-scale ISA semantics and axiomatic concurrency modelshttps://www.cl.cam.ac.uk/~pes20/isla/isla-cav2021-extended.pdf
bibhttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_bib.html#isla-cav
doihttp://dx.doi.org/10.1007/978-3-030-81685-8\_14
pdfhttps://www.cl.cam.ac.uk/~pes20/isla/isla-cav2021-extended.pdf
httphttps://doi.org/10.1007/978-3-030-81685-8\_14
abstracthttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_abstracts.html#isla-cav
ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPShttp://www.cl.cam.ac.uk/users/pes20/sail/sail-popl2019.pdf
bibhttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_bib.html#sail-popl2019
doihttp://dx.doi.org/10.1145/3290384
supplementary materialhttp://www.cl.cam.ac.uk/users/pes20/sail/popl2019.html
project pagehttp://www.cl.cam.ac.uk/~pes20/sail/
pdfhttp://www.cl.cam.ac.uk/users/pes20/sail/sail-popl2019.pdf
abstracthttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_abstracts.html#sail-popl2019
Formalisation of MiniSail in the Isabelle Theorem Proverhttp://www.cl.cam.ac.uk/~pes20/sail/arw18_mpew2.pdf
bibhttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_bib.html#sail-arw18-minisail
project pagehttp://www.cl.cam.ac.uk/~pes20/sail/
pdfhttp://www.cl.cam.ac.uk/~pes20/sail/arw18_mpew2.pdf
abstracthttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_abstracts.html#sail-arw18-minisail
Detailed Models of Instruction Set Architectures: From Pseudocode to Formal Semanticshttp://www.cl.cam.ac.uk/~pes20/sail/2018-04-12-arw-paper.pdf
bibhttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_bib.html#sail-arw18
project pagehttp://www.cl.cam.ac.uk/~pes20/sail/
pdfhttp://www.cl.cam.ac.uk/~pes20/sail/2018-04-12-arw-paper.pdf
abstracthttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_abstracts.html#sail-arw18
Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and Operational Models for ARMv8http://www.cl.cam.ac.uk/~pes20/armv8-mca/armv8-mca-draft.pdf
bibhttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_bib.html#armv8-mca
doihttp://dx.doi.org/10.1145/3158107
project pagehttp://www.cl.cam.ac.uk/~pes20/armv8-mca/
erratahttps://www.cl.cam.ac.uk/~pes20/armv8-mca/errata.html
pdfhttp://www.cl.cam.ac.uk/~pes20/armv8-mca/armv8-mca-draft.pdf
abstracthttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_abstracts.html#armv8-mca
Mixed-size Concurrency: ARM, POWER, C/C++11, and SChttp://www.cl.cam.ac.uk/~pes20/popl17/mixed-size.pdf
bibhttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_bib.html#mixed17
doihttp://dx.doi.org/10.1145/3009837.3009839
project pagehttp://www.cl.cam.ac.uk/users/pes20/popl17/
pdfhttp://www.cl.cam.ac.uk/~pes20/popl17/mixed-size.pdf
abstracthttps://github.com/lowRISC/sail/blob/sail2/topic.ISA_semantics_abstracts.html#mixed17
Modelling the ARMv8 architecture, operationally: concurrency and ISAhttp://www.cl.cam.ac.uk/~pes20/popl16-armv8/top.pdf
doihttp://dx.doi.org/10.1145/2837614.2837615
project pagehttp://www.cl.cam.ac.uk/~sf502/popl16/index.html
pdfhttp://www.cl.cam.ac.uk/~pes20/popl16-armv8/top.pdf
An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessorshttp://www.cl.cam.ac.uk/~pes20/micro-48-2015.pdf
doihttp://dx.doi.org/10.1145/2830772.2830775
pdfhttp://www.cl.cam.ac.uk/~pes20/micro-48-2015.pdf
https://github.com/lowRISC/sail#funding
REMS: Rigorous Engineering for Mainstream Systemshttp://www.cl.cam.ac.uk/users/pes20/rems
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