René's URL Explorer Experiment

{"@context":"https://schema.org","@type":"DiscussionForumPosting","headline":"Experience Solving Common Setup and Vivado Timing Issues","articleBody":"I would like to share my issues and my solution for each problem\n\n- part 0 environment preparation (create conda envionment)\n\t- problem --\u003e ModuleNotFoundError: No module named 'notebook.extensions'\n\t\t- solution --\u003e Edit environment.yml from “notebook” to “notebook\u003c7”\n\t- problem --\u003e In part7, for who using xilinx toolchain \u003e= 2020.2, will not have vivado_hls\n\t\t- solution --\u003e install HLS4ML from this pull request https://github.com/fastmachinelearning/hls4ml/pull/1134 instead (This will give you \"vitisAcceleratorBackend\")\n\t\t\n\t\t\n- part 3 compression\n\t- problem --\u003e ModuleNotFoundError: No module named 'tensorflow_model_optimization'\n\t\t- solution --\u003e  ``` pip install -U tensorflow-model-optimization ```\n\t\t\n- part 5 bdt\n\t- problem --\u003e on pynq z2, the vivado say \"can't replace all shape\"\n\t \t- since the hls design set the target clock at 200 MHz, the vivado can't place all shape\n\t \t- solution --\u003e set the hls4ml target clock to 50 MHz\n\t \t- using this code \n\t \t\t- ```  pynq_model_cfg['ClockPeriod'] = 20  # set the clock period to 20ns ```\n               - the code should be \n```python\npynq_model_cfg = conifer.backends.xilinxhls.auto_config()\npynq_model_cfg['OutputDir'] = 'model_5_pynq'  # choose a new project directory\npynq_model_cfg['ProjectName'] = 'conifer_jettag'\npynq_model_cfg['XilinxPart'] = 'xc7z020clg400-1'\npynq_model_cfg['ClockPeriod'] = 20  # set the clock period to 20ns\npynq_model_cfg['AcceleratorConfig'] = {\n    'Board': 'pynq-z2',  # choose a pynq-z2 board\n    'InterfaceType': 'float',  # floating point for the data I/O (this is default)\n}\n\n# print the config\nprint('Modified Configuration\\n' + '-' * 50)\nprint(json.dumps(pynq_model_cfg, indent=2))\nprint('-' * 50)\n```\n\n\n- part 7a\n\t- problem --\u003e on vivado throw the critical warning \"Timing constraints are not met\"\n\t\t- solution ---\u003e it \"ultrascale plus block\" -\u003e \"CLock Configuration\" -\u003e \"Output Clocks\" -\u003e \"Low Power Domain Clock\" -\u003e PL0 set to 50\n\n![Image](https://github.com/user-attachments/assets/7bee9447-e646-45d5-aa3a-50c6ef632a5b)\n","author":{"url":"https://github.com/Tanawin1701d","@type":"Person","name":"Tanawin1701d"},"datePublished":"2025-07-04T05:45:01.000Z","interactionStatistic":{"@type":"InteractionCounter","interactionType":"https://schema.org/CommentAction","userInteractionCount":0},"url":"https://github.com/106/hls4ml-tutorial/issues/106"}