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Title: Mcl86jr correctness fixes by mx-shift · Pull Request #55 · MicroCoreLabs/Projects · GitHub

Open Graph Title: Mcl86jr correctness fixes by mx-shift · Pull Request #55 · MicroCoreLabs/Projects

X Title: Mcl86jr correctness fixes by mx-shift · Pull Request #55 · MicroCoreLabs/Projects

Description: Ted Fried's MicroCore Labs Projects - FPGA CPU cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8, MCL6809, XTMax, MCL8080+ - Mcl86jr correctness fixes by mx-shift · Pull Request #55 · MicroCoreLabs/Projects

Open Graph Description: A variety of verilog and microcode fixes to match Intel 8088 documented behavior. The currently released version (with microcode V4) hangs before reaching TOPBENCH's main menu. Tracking down ...

X Description: A variety of verilog and microcode fixes to match Intel 8088 documented behavior. The currently released version (with microcode V4) hangs before reaching TOPBENCH's main menu. Tracking d...

Opengraph URL: https://github.com/MicroCoreLabs/Projects/pull/55

X: @github

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Domain: github.com

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May 21, 2026https://github.com/MicroCoreLabs/Projects/pull/55#issue-4491831496
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May 9, 2026 22:40https://github.com/MicroCoreLabs/Projects/pull/55#commits-pushed-801c16c
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BIU: ack HALT immediately without running a bus cyclehttps://github.com/MicroCoreLabs/Projects/pull/55/commits/801c16c4fa6c778917049fa75eeecfbb944e973d
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BIU: stage CS register update so it commits atomically with pfq_addr_inhttps://github.com/MicroCoreLabs/Projects/pull/55/commits/ae1b2ef21cea6e1563a250b07cbe264a87e4966f
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Add microcode assemblerhttps://github.com/MicroCoreLabs/Projects/pull/55/commits/729eeb6d9e5ec6d8eb32a6879cfe2800a04e00c1
729eeb6https://github.com/MicroCoreLabs/Projects/pull/55/commits/729eeb6d9e5ec6d8eb32a6879cfe2800a04e00c1
https://github.com/mx-shift
V5 microcode: STORE/RESTORE_SEG_PREFIX use r2 scratch, not AF flaghttps://github.com/MicroCoreLabs/Projects/pull/55/commits/21663c6068907f7b89e105d51cff520432594eab
21663c6https://github.com/MicroCoreLabs/Projects/pull/55/commits/21663c6068907f7b89e105d51cff520432594eab
https://github.com/mx-shift
V6 microcode: don't skip INT poll for non-SS segment loadshttps://github.com/MicroCoreLabs/Projects/pull/55/commits/060bf4e279adc86f75cc2b631479f1c8c8606e96
060bf4ehttps://github.com/MicroCoreLabs/Projects/pull/55/commits/060bf4e279adc86f75cc2b631479f1c8c8606e96
https://github.com/mx-shift
BIU: proper 8086 offset-wrap on word-read byte-2 addresshttps://github.com/MicroCoreLabs/Projects/pull/55/commits/063896efcbe39684d851006f29d5c9e10462a9b9
063896ehttps://github.com/MicroCoreLabs/Projects/pull/55/commits/063896efcbe39684d851006f29d5c9e10462a9b9
https://github.com/mx-shift
V7 microcode + eu.v: IRET interrupt-recognition fixhttps://github.com/MicroCoreLabs/Projects/pull/55/commits/5c3c7e7ab0852f0dda31bf309e4e9cc6a519f177
5c3c7e7https://github.com/MicroCoreLabs/Projects/pull/55/commits/5c3c7e7ab0852f0dda31bf309e4e9cc6a519f177
https://github.com/mx-shift
V8 microcode: AAM/AAD flags from AL, not full AXhttps://github.com/MicroCoreLabs/Projects/pull/55/commits/ff88e398aa92c889470ffb060a82b2cd01f03053
ff88e39https://github.com/MicroCoreLabs/Projects/pull/55/commits/ff88e398aa92c889470ffb060a82b2cd01f03053
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May 21, 2026 04:51https://github.com/MicroCoreLabs/Projects/pull/55#event-25788199113
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