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Title: GitHub - GSTL-ITU/HORNET-RV32IMF-For-AI-Applications: A custom RISC-V (RV32IMF) soft-core, "Hornet", implemented on Artix-7 FPGA for Edge AI and Network Intrusion Detection. Β· GitHub

Open Graph Title: GitHub - GSTL-ITU/HORNET-RV32IMF-For-AI-Applications: A custom RISC-V (RV32IMF) soft-core, "Hornet", implemented on Artix-7 FPGA for Edge AI and Network Intrusion Detection.

X Title: GitHub - GSTL-ITU/HORNET-RV32IMF-For-AI-Applications: A custom RISC-V (RV32IMF) soft-core, "Hornet", implemented on Artix-7 FPGA for Edge AI and Network Intrusion Detection.

Description: A custom RISC-V (RV32IMF) soft-core, "Hornet", implemented on Artix-7 FPGA for Edge AI and Network Intrusion Detection. - GSTL-ITU/HORNET-RV32IMF-For-AI-Applications

Open Graph Description: A custom RISC-V (RV32IMF) soft-core, "Hornet", implemented on Artix-7 FPGA for Edge AI and Network Intrusion Detection. - GSTL-ITU/HORNET-RV32IMF-For-AI-Applications

X Description: A custom RISC-V (RV32IMF) soft-core, "Hornet", implemented on Artix-7 FPGA for Edge AI and Network Intrusion Detection. - GSTL-ITU/HORNET-RV32IMF-For-AI-Applications

Mail addresses
tekiny20@itu.edu.tr
ozkanah19@itu.edu.tr
tekiny20@itu.edu.tr
ozkanah19@itu.edu.tr

Opengraph URL: https://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications

X: @github

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https://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#design-and-implementation-of-risc-v-based-core-for-ai-applications
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https://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#-table-of-contents
Design and Implementation of RISC-V-Based Core For AI Applicationshttps://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#design-and-implementation-of-risc-v-based-core-for-ai-applications
πŸ“– Table of Contentshttps://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#-table-of-contents
πŸ› System Architecturehttps://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#-system-architecture
πŸš€ About the Projecthttps://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#-about-the-project
πŸ— System Design & Verificationhttps://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#-system-design--verification
1. RTL Simulation Flowhttps://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#1-rtl-simulation-flow
2. Hardware-in-the-Loop (HIL) Flowhttps://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#2-hardware-in-the-loop-hil-flow
πŸ“‚ Repository Structurehttps://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#-repository-structure
πŸ›  Prerequisites & Toolchainhttps://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#-prerequisites--toolchain
Hardware Requirements:https://github.com/GSTL-ITU/HORNET-RV32IMF-For-AI-Applications#hardware-requirements
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