Title: Pulse · GSTL-ITU/HORNET-RV32IMF · GitHub
Open Graph Title: Pulse · GSTL-ITU/HORNET-RV32IMF
X Title: Pulse · GSTL-ITU/HORNET-RV32IMF
Description: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - Pulse · GSTL-ITU/HORNET-RV32IMF
Open Graph Description: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - Pulse · GSTL-ITU/HORNET-RV32IMF
X Description: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - Pulse · GSTL-ITU/HORNET-RV32IMF
Opengraph URL: https://github.com/GSTL-ITU/HORNET-RV32IMF
X: @github
Domain: github.com
| route-pattern | /:user_id/:repository/pulse(/:period) |
| route-controller | repositories |
| route-action | pulse |
| fetch-nonce | v2:84a98106-8a43-3aff-6b1c-d8d1729a2716 |
| current-catalog-service-hash | b4d8436665c5448282b6f4eacc6394e6e8801de97cb226acdca9da20ae59be92 |
| request-id | EC48:32D923:9C3BB2D:D3A36D8:6A4BAC5E |
| html-safe-nonce | a877309fbacddb1fd7d6a70c5082d588a7a2f527558ed21490bcea49732bfb33 |
| visitor-payload | eyJyZWZlcnJlciI6IiIsInJlcXVlc3RfaWQiOiJFQzQ4OjMyRDkyMzo5QzNCQjJEOkQzQTM2RDg6NkE0QkFDNUUiLCJ2aXNpdG9yX2lkIjoiMzAxMzM2MzMzMTk5ODQ2NDk0IiwicmVnaW9uX2VkZ2UiOiJpYWQiLCJyZWdpb25fcmVuZGVyIjoiaWFkIn0= |
| visitor-hmac | 4f879759e483f3cabe7b158366ed6cf486beae7b86b56a6a7973f9412437e799 |
| hovercard-subject-tag | repository:1184065946 |
| github-keyboard-shortcuts | repository,copilot |
| google-site-verification | Apib7-x98H0j5cPqHWwSMm6dNU4GmODRoqxLiDzdx9I |
| octolytics-url | https://collector.github.com/github/collect |
| analytics-location | / |
| fb:app_id | 1401488693436528 |
| apple-itunes-app | app-id=1477376905, app-argument=https://github.com/GSTL-ITU/HORNET-RV32IMF/pulse |
| twitter:image | https://opengraph.githubassets.com/222d6cf3b299052bbe4a64330ee53e3457e67628d7262e8b18e3d7ff0de6c5ad/GSTL-ITU/HORNET-RV32IMF |
| twitter:card | summary_large_image |
| og:image | https://opengraph.githubassets.com/222d6cf3b299052bbe4a64330ee53e3457e67628d7262e8b18e3d7ff0de6c5ad/GSTL-ITU/HORNET-RV32IMF |
| og:image:alt | A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - Pulse · GSTL-ITU/HORNET-RV32IMF |
| og:image:width | 1200 |
| og:image:height | 600 |
| og:site_name | GitHub |
| og:type | object |
| hostname | github.com |
| expected-hostname | github.com |
| None | 3ede370c1d797b0693475db9bb4298020548dcae9c98a2f071d54aaf1b4e9faa |
| turbo-cache-control | no-cache |
| go-import | github.com/GSTL-ITU/HORNET-RV32IMF git https://github.com/GSTL-ITU/HORNET-RV32IMF.git |
| octolytics-dimension-user_id | 241955837 |
| octolytics-dimension-user_login | GSTL-ITU |
| octolytics-dimension-repository_id | 1184065946 |
| octolytics-dimension-repository_nwo | GSTL-ITU/HORNET-RV32IMF |
| octolytics-dimension-repository_public | true |
| octolytics-dimension-repository_is_fork | false |
| octolytics-dimension-repository_network_root_id | 1184065946 |
| octolytics-dimension-repository_network_root_nwo | GSTL-ITU/HORNET-RV32IMF |
| turbo-body-classes | logged-out env-production page-responsive |
| disable-turbo | false |
| browser-stats-url | https://api.github.com/_private/browser/stats |
| browser-errors-url | https://api.github.com/_private/browser/errors |
| release | af627ba2b0ed5351c6d1b8e04fdbe893325c237f |
| ui-target | full |
| theme-color | #1e2327 |
| color-scheme | light dark |
Links:
Viewport: width=device-width