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Title: Issues · GSTL-ITU/HORNET-RV32IMF · GitHub

Open Graph Title: Issues · GSTL-ITU/HORNET-RV32IMF

X Title: Issues · GSTL-ITU/HORNET-RV32IMF

Description: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - Issues · GSTL-ITU/HORNET-RV32IMF

Open Graph Description: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - Issues · GSTL-ITU/HORNET-RV32IMF

X Description: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - Issues · GSTL-ITU/HORNET-RV32IMF

Opengraph URL: https://github.com/GSTL-ITU/HORNET-RV32IMF

X: @github

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Domain: github.com

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og:image:altA 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - Issues · GSTL-ITU/HORNET-RV32IMF
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