Title: GitHub - GSTL-ITU/HORNET-RV32IMF: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. · GitHub
Open Graph Title: GitHub - GSTL-ITU/HORNET-RV32IMF: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals.
X Title: GitHub - GSTL-ITU/HORNET-RV32IMF: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals.
Description: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - GSTL-ITU/HORNET-RV32IMF
Open Graph Description: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - GSTL-ITU/HORNET-RV32IMF
X Description: A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals. - GSTL-ITU/HORNET-RV32IMF
Mail addresses
tekiny20@itu.edu.tr
eroglud20@itu.edu.tr
Opengraph URL: https://github.com/GSTL-ITU/HORNET-RV32IMF
X: @github
Domain: github.com
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